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W83176R-735 Data Sheet WINBOND 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET
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Publication Release Date: April 13, 2005 Revision 1.1
W83176R-735
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 1 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 2 5.1 5.2 6. 6.1 6.2 7. 7.1 7.2 7.3 7.4 8. 8.1 8.2 8.3 9. 10. 11. 12. Clock Outputs ................................................................................................................. 3 Power Pins...................................................................................................................... 3 Register 5: Output Control (1 = Active, 0 = Inactive) (Default = FFH)............................ 4 Register 6: Output Control (1 = Active, 0 = Inactive) (Default = FFH)............................ 4 Block Write Protocol ....................................................................................................... 5 Block Read Protocol ....................................................................................................... 5 Byte Write Protocol ......................................................................................................... 5 Byte Read Protocol ......................................................................................................... 5 Absolute Maximum Ratings ............................................................................................ 6 A.C. Characteristics ........................................................................................................ 6 D.C. Characteristics ........................................................................................................ 6
REGISTER 0 ~ REGISTER 4 RESERVED ................................................................................ 4
ACCESS INTERFACE ................................................................................................................ 5
SPECIFICATIONS ...................................................................................................................... 6
ORDERING INFORMATION....................................................................................................... 6 HOW TO READ THE TOP MARKING ........................................................................................ 7 PACKAGE DRAWING AND DIMENSIONS ................................................................................ 8 REVISION HISTORY .................................................................................................................. 9
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W83176R-735
1. GENERAL DESCRIPTION
The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735 can support 3 D.D.R. DRAM DIMMs. The W83176R-735 provides I2C serial bus interface to program the registers to enable or disable each clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply.
2. FEATURES
* * * * * * * * Zero-delay clock outputs Feedback pins for synchronous Supports up to 3 D.D.R. DIMMs One pairs of additional outputs for feedback Low Skew outputs (<100 pS) Supports 400 MHz D.D.R. SDRAM I2C 2-Wire serial interface and supports Byte or Block Date RW Packaged in 48-pin SSOP
3. PIN CONFIGURATION
GND C LK C 0 C LK T 0 VDD C LK T 1 C LK C 1 GND GND C LK C 2 C LK T 2 VDD * S C LK C LK _IN T N /C VDD AVDD AGND GND C LK C 3 C LK T 3 VDD C LK T 4 C LK C 4 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND C LK C 5 C LK T 5 VDD C LK T 6 C LK C 6 GND GND C LK C 7 C LK T 7 VDD SDATA * N /C F B _IN T VDD F B _O U TT NC GND C LK C 8 C LK T 8 VDD C LK T 9 C LK C 9 GND
*: Internal pull-up resistor 120K to VDD
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Publication Release Date: April 13, 2005 Revision 1.1
W83176R-735
4. BLOCK DIAGRAM
5. PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin *- Internal 120K pull-up
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W83176R-735
5.1 Clock Outputs
SYMBOL PIN I/O FUNCTION
CLKC[9:0] CLKT[9:0] SDATA * SCLK * CLK_INT NC FB_OUTT
26, 30, 40, 43, 47, 23, 19, 9, 6, 2 27, 29, 39, 44, 46, 22, 20, 10, 5, 3 37 12 13 14, 32, 36 33
OUT OUT I/O IN IN NONE OUT
Complementory Clocks of differential pair outputs True Clocks of differential pair outputs Serial data of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd Serial clock of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd True reference clock input, 3.3V tolerant input Not connected True Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. True Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error.
FB_INT
35
IN
5.2 Power Pins
SYMBOL PIN FUNCTION
GND VDD AVDD AGND
1, 7, 8, 18, 24, 25, Ground 31, 41, 42, 48 4, 11, 15, 21, 28, 34, 38, 45 16 17 Power Supply 2.5V Analog power supply, 2.5V Analog ground
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Publication Release Date: April 13, 2005 Revision 1.1
W83176R-735
6. REGISTER 0 ~ REGISTER 4 RESERVED 6.1 Register 5: Output Control (1 = Active, 0 = Inactive) (Default = FFH)
BIT @POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
2, 3 6, 5 9, 10 19, 20 23, 22 26, 27 -
CLKC0, CLKT0 output control CLKC1, CLKT1 output control CLKC2, CLKT2 output control CLKC3, CLKT3 output control CLKC4, CLKT4 output control CLKC9, CLKT9 output control Reserved Reserved
6.2 Register 6: Output Control (1 = Active, 0 = Inactive) (Default = FFH)
BIT @POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
30, 29 40, 39 43, 44 47, 46 -
Reserved Reserved Reserved CLKC8, CLKT8 output control CLKC7, CLKT7 output control CLKC6, CLKT6 output control CLKC5, CLKT5 output control Reserved
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W83176R-735
7. ACCESS INTERFACE
The W83176R-735 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83176R-735 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C write address is defined at 0xD4. The I2C read address is defined at 0xD5.
Block Read and Block Write Protocol
7.1 Block Write Protocol
7.2 Block Read Protocol
## In block mode, the command code must filled 00H
7.3 Byte Write Protocol
7.4 Byte Read Protocol
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Publication Release Date: April 13, 2005 Revision 1.1
W83176R-735
8. SPECIFICATIONS
8.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
SYMBOL PARAMETER RATING
VDD, AVDD TSTG TB TA
Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature
-0.5V to +3.6V -65C to +150C -55C to +125C 0C to +70C
8.2 A.C. Characteristics
VDD = AVDD = 2.5V 5 %, TA = 0C to +70C, Test load = 10 pF
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
Operating Clock Frequency Input Clock Duty Cycle Dynamic Supply Current Cycle to Cycle Jitter Output to Output Skew Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Output Differential-pair Crossing Voltage
FIN Dtin Idd CCjitter Tskew Tor Tof Dtot Voc
100 40
200 60 300 200
MHz % mA pS pS pS pS % V Fin =100 to 200 MHz Fout =100 to 200 MHz Fout =100 to 200 MHz Fout =100 to 200 MHz Fout =100 to 200 MHz Fout =100 to 200 MHz Fout =100 to 200 MHz
650 650 45 (VDD/2) -0.2
VDD/ 2
100 950 950 55 (VDD/2) + 0.2
8.3 D.C. Characteristics
VDD = AVDD = 2.5V 5%, TA = 0C to +70C
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
SDATA, SCLK Input Low Voltage SDATA, SCLK Input High Voltage CLKIN, FBIN Input Voltage Low CLKIN, FBIN Input Voltage High Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
SVIL SVIH VIL VIH CIN COUT LIN 2.1 2.2
1.0 0.4 5 6 7
Vdc Vdc Vdc Vdc pF pF nH Fin = 100 to 200 MHz Fin = 100 to 200 MHz
9. ORDERING INFORMATION
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W83176R-735
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83176R_735
48-pin SSOP
Commercial, 0C to +70C
10. HOW TO READ THE TOP MARKING
W83176R-735 28051234 342GB
1st line: Winbond logo and the type number: W83176R-735 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G B 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: April 13, 2005 Revision 1.1
W83176R-735
11. PACKAGE DRAWING AND DIMENSIONS
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W83176R-735
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
n.a. 0.5 1.0 1.1 12/18/03 05/06/04 04/13/2005 3.7
All of the versions before 0.50 are for internal use. Correction IC version, add register default value and correction some description and default value Update to web Add disclaimer
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: April 13, 2005 Revision 1.1

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